View PI6CFGL201BZDIE_8618277.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 www.pericom.com pi6cfgl201b revb 03/16/16 pi6cfgl201b block diagram description te pi6cfgl201b is a 2-output very low power 100mhz fre - quency generator for pcie gen 1, 2 and 3 applications with inte - grated output terminations providing zo=100. te device has 2 output enables for clock management and supports 2 diferent spread spectrum levels in addtion to spread of. te device also has one 1.8v lvcmos ref1.8 output. features ? ? 25mhz crystal or reference clock input ? ? 100mhz low power hcsl or lvds compatible outputs ? ? pcie 3.0, 2.0 and 1.0 compliant ? ? selectable spread spectrum of -0.25%, -0.5% and no spread ? ? programmable output amplitude and slew rate ? ? cycle-to-cycle jitter (typ.) ~ 30ps ? ? supply voltage of 3.3v+/-10% ? ? output supply voltage of 1.8v (1.05v to 3.6v supported) ? ? industrial ambient operating temperature ? ? available in lead-free package: 24-tqfn 2-output low power pcie gen 1-2-3 clock generator + i + u t osc sdata_3.3 sclk_3.3 ss capable pll control logic xtal_in or ref clk ref1.8 oe(1:0)# sadr ss_en_tri ckpwrgd_pd# + clk0 clk0# clk1 clk1# xtal_out applications ? ? pcie 3.0/2.0/1.0 clock generation pin configuration (24-pin tqfn) 7 8 9 10 11 12 13 14 15 16 17 18 192021222324 1 2 3 4 5 6 sadr/ref1.8 vddref1.8 gnddig vdddig3.3 sclk_3.3 gnd vddo1.8 oe0# clk0 clk0# gnda vddxtal xtal_out ss_en_tri xtal_in gndxtal ckpwrgd_pd# gnd clk1# vddo1.8 oe1# clk1 vdda3.3 sdata_3.3 all trademarks are property of their respective owners. 15-0134
2 www.pericom.com pi6cfgl201b revb 03/16/16 smbus address selection table sadr address + read/write bit state of sadr on frst application of ckpwrgd_pd# 0 1101000 1/0 1 1101010 1/0 power management table ckpwrgd_pd# smbus oe bit clkx ref1.8 true o/p comp. o/p 0 x low low hi-z 1 1 1 running running running 1 0 low low low note: 1. ref1.8 is hi-z until the 1st assertion of ckpwrgd_pd# high. after this, when ckpwrg_pd# is low, ref1.8 is low. output input typ. 6us first rise edge ckpwrgd_pd# sadr/ref1.8 ckpwrgd_pd# oe (pin) oe (smbus bit) clkx true o/p comp. o/p 0 x x low low 1 0 0 low low 1 0 1 running running 1 1 0 low low 1 1 1 low low all trademarks are property of their respective owners. pi6cfgl201b 2-output low power pcie gen 1-2-3 clock generator 15-0134
3 www.pericom.com pi6cfgl201b revb 03/16/16 pin description pin# pin name ty pe description 1 xtal_in input crystal input or reference input clock, nominally 25.00mhz. 2 xtal_out output crystal output. 3 vddxtal power 3.3v power supply for xtal. 4 sadr/ref1.8 input/output latch to select smbus address/1.8v lvcmos ref1.8 output. tis pin has an internal pull-down. 5 vddref1.8 power power supply for the ref1.8 output 6 gnddig power ground pin for digital circuitry 7 vdddig3.3 power 3.3v digital power (dirty power) 8 sclk_3.3 input clock pin of smbus circuitry, 3.3v tolerant. 9 sdata_3.3 input/output data pin for smbus circuitry, 3.3v tolerant. 10 gnd power ground pin. 11 vddo1.8 power power supply, nominal 1.8v, range 1.05v~3.3v. 12 oe0# input active low input for enabling clk0 pair 0. tis pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 13 clk0 output diferential true clock output 14 clk0# output diferential complementary clock output 15 gnda power ground pin for the pll core. 16 vdda3.3 power 3.3v power for the pll core. 17 clk1 output diferential true clock output 18 clk1# output diferential complementary clock output 19 oe1# input active low input for enabling clk1 pair 1. tis pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 20 vddo1.8 power power supply, nominal 1.8v, range 1.05v~3.3v. 21 gnd power ground pin. 22 ckpwrgd_ pd# input input notifes device to sample latched inputs and start up on frst high assertion. low enters power down mode, subsequent high assertions exit power down mode. tis pin has internal pull-up resistor. 23 ss_en_tri input latched select input to select spread spectrum amount at initial power up : 1 = -0.5% spread, m = -0.25%, 0 = spread of tis pin has an internal pull-down. 24 gndxtal power gnd for xtal typical crystal requirement parameter test conditions min. ty pe max. units mode of oscillation fundamental frequency 25 mhz equivalent series resistance (esr) shunt capacitance pf recommended crystal specification a) fl2500047, smd 3.2x2.5(4p), 25mhz, cl=18pf, +/-20ppm, http://www.pericom.com/pdf/datasheets/se/fl.pdf b) fy2500091, smd 5x3.2(4p), 25mhz, cl=18pf, +/-30ppm, http://www.pericom.com/pdf/datasheets/se/fy_f9.pdf all trademarks are property of their respective owners. pi6cfgl201b 2-output low power pcie gen 1-2-3 clock generator 15-0134
4 www.pericom.com pi6cfgl201b revb 03/16/16 electrical characteristicsCcurrent consumption (t a = -40~85 o c; vdd = 3.3v +/-10%; vddo = 1.8v +/-10% , see test loads for loading conditions) symbol parameters condition min. ty pe max. units i dda operating supply current 1 vdda3.3, pll mode, core current consumption 29 38 ma i ddop vddo, output only current consumption. all outputs active 6 8 ma i ddtotal total current consumption. all outputs active @100mhz 35 46 ma i ddsusp suspend supply current 1 vddxxx, ckpwrgd_pd# = 0, wake-on-lan enabled 4.5 8 ma i ddpd powerdown current 1,2 ckpwrgd_pd#=0 1.3 1.8 ma notes: 1. guaranteed by design and characterization, not 100% tested in production. 2. assuming ref1.8 is not running in power down state. electrical characteristicsCdifferential output duty cycle, jitter, and skew characterisitics (t a = -40~85 o c; vdd = 3.3v +/-10%; vddo = 1.8v +/-10% , see test loads for loading conditions) symbol parameters condition min. ty pe max. units t dc duty cycle 1 measured diferentially, pll mode 45 55 % t sk skew, output to output 1 v t = 50% 50 ps t jcyc-cyc jitter, cycle to cycle 1 pll mode 50 ps notes: 1. guaranteed by design and characterization, not 100% tested in production. supply voltage to ground potential (all vddx) ................................ 4.6v all inputs and output ..................................................... -0.5v tov dd +0.5v ambient operating temperature ........................................... -40 to +85c storage temperature .......................................................... C65c to +150c esd protection (input) ........................................................... 2000v(hbm) note: stresses greater than those listed under maximum rat - ings may cause permanent damage to the device. tis is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may afect reliability. maximum ratings (above which useful life may be impaired. for user guidelines, not tested.) all trademarks are property of their respective owners. pi6cfgl201b 2-output low power pcie gen 1-2-3 clock generator 15-0134
5 www.pericom.com pi6cfgl201b revb 03/16/16 electrical characteristicsCinput/supply/common parameters (based on t a = -40~85 o c ; vdd = 3.3v +/-10%; vddo = 1.8v +/-10% , see test loads for loading conditions) symbol parameters condition min. ty pe max. units v ddx supply voltage 1 supply voltage for core, analog 3.0 3.3 3.6 v v ddo supply voltage 1 supply voltage outputs 1.05 1.8 3.3 v t a ambient operating temperature 1 -40 25 85 c v ih input high voltage 1 single-ended inputs, except smbus, ss_en_tri 0.65 v dd v dd +0.3 v v im input mid voltage 1 ss_en_tri 0.4 v dd 0.6 v dd v v il input low voltage 1 single-ended inputs, except smbus, ss_en_tri -0.3 0.35 v dd v v t+ schmitt trigger postive going treshold voltage 1 single-ended inputs, except ss_en_tri 0.5 v dd 0.6 v dd v v t- schmitt trigger negative going treshold voltage 1 single-ended inputs, except ss_en_tri 0.4 v dd 0.5 v dd v v h hysteresis voltage 1 v t+ - v t- 0.05 v dd 0.2 v dd v v oh output high voltage 1 single-ended outputs, except smbus. i oh = -2ma v dd -0.45 v v ol outputt low voltage 1 single-ended outputs, except smbus. i ol = -2ma 0.45 v i in input current 1 single-ended inputs, v in = gnd, v in = vdd (exclude xtal_in pin) -5 5 ua i inp single-ended inputs v in = 0 v; inputs with internal pull-up resistors v in = vdd; inputs with internal pull-down resistors -200 200 ua fn input frequency 1 xtal, or xtal_in 23 25 26 mhz lpin pin inductance 1 7 nh c in capacitance 1 control inputs 1.5 5 pf cout output pin capacitance 6 pf t stab clock output stabiliza - tion 1, 2 from v dd power-up and afer input clock stabilization or de-assertion of ckpwrgd_ pd# to 1st clock 0.6 1 ms f modin input ss modulation frequency 1 allowable frequency (triangular modulation) 30 31.500 33 khz t latoe# oe# latency 1, 3 clk start afer oe# assertion clk stop afer oe# deassertion 1 3 clocks t drvpd tdrive_pd# 1, 3 clk output enable afer ckpwrgd_pd# de-assertion 300 us all trademarks are property of their respective owners. pi6cfgl201b 2-output low power pcie gen 1-2-3 clock generator 15-0134
6 www.pericom.com pi6cfgl201b revb 03/16/16 symbol parameters condition min. ty pe max. units electrical characteristicsCinput/supply/common parameters (based on t a = -40~85 o c ; vdd = 3.3v +/-10%; vddo = 1.8v +/-10% , see test loads for loading conditions) t f fall time 1, 2 control inputs 5 ns t r rise time 1, 2 control inputs 5 ns v ilsmb smbus input low voltage 1 0.8 v v ihsmb smbus input high voltage 1 2.1 3.6 v v olsmb smbus output low voltage 1 @ i pullup 0.4 v i pullup smbus sink current 1 @ v ol 4 ma v ddsmb nominal bus voltage 1 3.3v bus voltage 2.7 3.6 v t rsmb sclk/sdata rise time 1 (max vil - 0.15) to (min vih + 0.15) 1000 ns t fsmb sclk/sdata fall time 1 (min vih + 0.15) to (max vil - 0.15) 300 ns f maxsmb smbus operating frequency 1, 5 maximum smbus operating frequency 400 khz electrical characteristicsCclk 0.7v low power hcsl outputs ( t a = -40~85 o c ; vdd = 3.3v +/-10%; vddo = 1.8v +/-10% , see test loads for loading conditions) symbol parameters condition min. ty pe max. units trf slew rate 1, 2, 3 scope averaging on 1.5v/ns setting 0.9 1.4 1.9 v/ns scope averaging on 3.0v/ns setting 1.8 2.9 4 v/ns trf slew rate matching 1, 2, 4 slew rate matching, scope averaging on 20 % v oh voltage hig h 1, 7 statistical measurement on single-ended signal using oscilloscope math function. (scope averaging on) 660 850 mv v ol voltage l ow 1, 7 -150 150 mv vmax ma x voltage 1 measurement on single ended signal using absolute value. (scope averaging of) 1150 mv vmin mi n voltage 1 -300 mv vsw ing vsw ing 1, 2, 7 scope averaging of 300 mv vcross_abs crossing voltage (abs) 1, 5, 7 scope averaging of 250 550 mv -vcross crossing voltage (var) 1, 6 scope averaging of 140 mv note: 1. guaranteed by design and characterization, not 100% tested in production. 2. measured from differential waveform 3. slew rate is measured through the vswing voltage range centered around differential 0v. this results in a +/-150mv window around differential 0v. 4. matching applies to rising edge rate for clock and falling edge rate for clock#. it is measured using a +/-75mv window centered on the average cross point where clock rising meets clock# falling. the median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calcula - tions. 5. vcross is defned as voltage where clock = clock# measured on a component test board and only applies to the differential rising edge (i.e. clock rising and clock# falling). 6. the total variation of all vcross measurements in any particular system. note that this is a subset of vcross_min/max (vcross absolute) allowed. the intent is to limit vcross induced modulation by setting -vcross to be smaller than vcross absolute. 7. at default smbus settings. note: 1. guaranteed by design and characterization, not 100% tested in production. 2. control input must be monotonic from 20% to 80% of input swing. input frequency capacitance 3. time from deassertion until outputs are >200 mv 4. the differential input clock must be running for the smbus to be active all trademarks are property of their respective owners. pi6cfgl201b 2-output low power pcie gen 1-2-3 clock generator 15-0134
7 www.pericom.com pi6cfgl201b revb 03/16/16 electrical characteristicsCphase jitter parameters (t a = -40~85 o c ; vdd = 3.3v +/-10%; vddo = 1.8v +/-10% , see test loads for loading conditions) symbol parameters condition min. ty pe industry limit units t jphpcieg1 1, 2, 3, 5 phase jitter, pci express pcie gen 1 30 86 ps (p-p) t jphpcieg2 1, 2, 5 pcie gen 2 low band 10khz < f < 1.5mhz 0.5 3 ps (rms) pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 2.2 3.1 ps (rms) t jphpcieg3 1, 2, 4, 5 pcie gen 3 (pll bw of 2-4mhz, cdr = 10mhz) 0.46 1 ps (rms) notes: 1. guaranteed by design and characterization, not 100% tested in production. 2. see http://www.pcisig.com for complete specs. 3. sample size of at least 100k cycles. this fgures extrapolates to 108ps pk-pk @ 1m cycles for a ber of 1-12. 4. calculated from intel-supplied clock jitter tool. 5. applies to all different outputs. electrical characteristicsCref1.8 (t a = -40~85 o c ; vdd = 3.3v +/-10%; vddo = 1.8v +/-10%, see test loads for loading conditions) symbol parameters condition min. ty pe max. units ppm long accuracy 1, 2 see tperiod min-max values 0 ppm t period clock period 1, 2 25 mhz output nominal 40 ns t rf1 rise/fall slew rate 1, 3 v oh = vdd-0.45v, v ol = 0.45v 0.5 2.5 v/ns t dc duty cycle 1, 4 v t = vddo/2 v 45 55 % t dcd duty cycle distortion 1, 5 v t = vddo/2 v 0 3 % t jc-c jitter, cycle to cycle 1, 4 v t = vddo/2 v 250 ps t jdbc1k noise foor 1, 4 1khz ofset -141 -120 dbc t jdbc10k noise foor 1, 4 10khz ofset to nyquist -150 -130 dbc t jphref jitter, phase 1, 4 12khz to 5mhz 0.46 1 ps (rms) notes: 1. guaranteed by design and characterization, not 100% tested in production. 2. all long term accuracy and clock period specifcations are guaranteed assuming that ref1.8 is trimmed to 25.00 mhz. 3. typical value occurs when ref1.8 slew rate is set to default value. 4. when driven by a crystal. 5. when driven by an external oscillator via the xtal_in pin. xtalk_out should be foating in this case. all trademarks are property of their respective owners. pi6cfgl201b 2-output low power pcie gen 1-2-3 clock generator 15-0134
8 www.pericom.com pi6cfgl201b revb 03/16/16 driving lvds inputs with the pi6cfgl201b component va lue receiver has termination receiver does not have termination r7a, r7b 10k 140 r8a, r8b 5.6k 75 cc 0.1 uf 0.1 uf vcm 1.2 volts 1.2 volts test loads rs r o 5 inches rs zo=100 2pf 2pf low-power hcsl differential output test load device alternate terminations r o zo device driving lvds cc cc r7a r7b r8a r8b 3.3v lvds clock input rs rs 22 r zo = 50 5pf ref1.8 output test load ref1.8 output all trademarks are property of their respective owners. pi6cfgl201b 2-output low power pcie gen 1-2-3 clock generator 15-0134
9 www.pericom.com pi6cfgl201b revb 03/16/16 serial data interface (smbus) tis part is a slave only device that supports blocks read and block write protocol using a single 7-bit address and read/write bit as shown below. read and write block transfers can be stopped afer any complete byte transfer by issuing stop. address assignment refer to smbus address selection table. data protocol (write) 1 bit 8 bits 1 8 bits 1 8 bits 1 8 bits 1 8 bits 1 1 bit start bit slave addr: d4 ack register ofset ack byte count=n ack data byte 0 ack data byte n-1 ack stop bit (read) 1 bit 8 bits 1 8 bits 1 1 8 bits 1 8 bits 1 8 bits 1 8 bits 1 1 bit start bit slave addr: d4 ack register ofset ack repeat start slave addr: d5 ack byte count=n ack data byte 0 ack data byte n-1 not ack stop bit note: 1. register ofset for indicating the starting register for indexed block write and indexed block read. byte count in write mode cannot be 0. all trademarks are property of their respective owners. pi6cfgl201b 2-output low power pcie gen 1-2-3 clock generator 15-0134
10 www.pericom.com pi6cfgl201b revb 03/16/16 smbus table: output enable register byte 0 bit name control function ty pe 0 1 default 7 reserved 1 6 reserved 1 5 reserved 1 4 reserved 1 3 reserved 1 2 oe1 output enable rw low/low enabled 1 1 oe0 output enable rw low/low enabled 1 0 reserved 1 smbus table: ss readback and vhigh control register byte 1 bit name control function ty pe 0 1 default 7 ssenrb1 ss enable readback bit1 r 00' for ss_en_tri = 0, '01' for ss_en_tri = 'm', '11 for ss_en_tri = '1' latch 6 ssenrb0 ss enable readback bit0 r latch 5 ssen_swcntrl enable sw control of ss rw ss control locked values in b1[4:3] control ss amount. 0 4 ssensw1 ss enable sofware ctl bit1 rw 1 00' = ss of, '01' = -0.25% ss, '10' = reserved, '11'= -0.5% ss 0 3 ssensw0 ss enable sofware ctl bit0 rw 1 0 2 reserved 1 1 amplitude 1 controls output amplitude rw 00 = 0.6v 01 = 0.7v 1 0 amplitude 0 rw 10= 0.8v 11 = 0.9v 0 smbus table: clk slew rate control register byte 2 bit name control function ty pe 0 1 default 7 reserved 1 6 reserved 1 5 reserved 1 4 reserved 1 3 reserved 1 2 slewratesel clk1 adjust slew rate of clk 1 rw 1.5v/ns 3.0v/ns 1 1 slewratesel clk0 adjust slew rate of clk0 rw 1.5v/ns 3.0v/ns 1 0 reserved 1 all trademarks are property of their respective owners. pi6cfgl201b 2-output low power pcie gen 1-2-3 clock generator 15-0134
11 www.pericom.com pi6cfgl201b revb 03/16/16 smbus table: ref1.8 control register byte 3 bit name control function ty pe 0 1 default 7 ref1.8 slew rate control rw 00 = 0.9v/ns 01 =1.3v/ns 0 6 rw 10 = 1.6v/ns 11 = 1.8v/ns 1 5 ref1.8 power down function wake-on-lan enable for ref1.8 rw ref1.8 does not run in power down ref1.8 runs in power down 0 4 ref1.8 oe ref1.8 output enable rw low enabled 1 3 reserved 1 2 reserved 1 1 reserved 1 0 reserved 1 byte 4 is reserved and reads back 'hff'. smbus table: revision and vendor id register byte 5 bit name control function ty pe 0 1 default 7 rid3 revision id r a rev = 0000 0 6 rid2 r 0 5 rid1 r 0 4 rid0 r 0 3 vid3 vendor id r 0 2 vid2 r 0 1 vid1 r 0 0 vid0 r 0 all trademarks are property of their respective owners. pi6cfgl201b 2-output low power pcie gen 1-2-3 clock generator 15-0134
12 www.pericom.com pi6cfgl201b revb 03/16/16 smbus table: device type/device id byte 6 bit name control function ty pe 0 1 default 7 dev ice ty pe1 dev ice ty pe r 00 = fgv, 01 = dbv, 10 = dmv, 11= reserved 0 6 dev ice ty pe 0 r 0 5 device id5 device id r 00010 binary or 02 hex 0 4 device id4 r 0 3 device id3 r 0 2 device id2 r 0 1 device id1 r 1 0 device id0 r 0 smbus table: byte count register byte 7 bit name control function ty pe 0 1 default 7 reserved 0 6 reserved 0 5 reserved 0 4 reserved 0 3 reserved 0 2 reserved 0 1 reserved 0 0 reserved 0 all trademarks are property of their respective owners. pi6cfgl201b 2-output low power pcie gen 1-2-3 clock generator 15-0134
13 www.pericom.com pi6cfgl201b revb 03/16/16 c1 27pf crystal?(c l? =?18pf) c2 27pf xtal_in xtal_out saronix-ecera fl2500047 application notes crystal circuit connection te following diagram shows crystal circuit connection with a parallel crystal. for the cl=18pf crystal, it is suggested to use c1= 27pf, c2= 27pf. c1 and c2 can be adjusted to fne tune to the target ppm of crystal oscillator according to diferent board layouts. crystal oscillator circuit x1 x2 cb c1 c2 cj rd rf cb pseudo sine cj cl= crystal spec. loading cap. cj = chip in/output cap. (3~5pf) cb = pcb trace/via cap. (2~4pf) c1,2 = load cap. components rd = drive level res. (100 ) asic final choose/trim c1=c2=2 *cl - (cb +cj) for the target +/-ppm example: c1=c2=2*(18pf) ? (4pf+5pf)=27pf thermal characteristics symbol parameters min. ty pe max. units ja termal resistance junction to ambient 54.4 o c/w jc termal resistance junction to case 40.8 o c/w all trademarks are property of their respective owners. pi6cfgl201b 2-output low power pcie gen 1-2-3 clock generator 15-0134
14 www.pericom.com pi6cfgl201b revb 03/16/16 pericom semiconductor corporation ? 1-800-435-2336 packaging mechanical: 24-pin tqfn (zd) date: 01/24/13 description: 24-contact, thin fine pitch quad flat no-lead (tqfn) package code: zd24 document control #: pd-2100 revision: a 13-0017 ordering information (1-3) ordering number package code package description operating temperature PI6CFGL201BZDIE zd 24-pin, tin fine pitch quad flat no-lead (tqfn) industrial PI6CFGL201BZDIEx zd 24-pin, tin fine pitch quad flat no-lead (tqfn), tape & reel industrial notes: 1. 1termal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. e = pb-free and green 3. adding an x sufx = tape/reel all trademarks are property of their respective owners. pi6cfgl201b 2-output low power pcie gen 1-2-3 clock generator 15-0134

▲Up To Search▲

Price & Availability of PI6CFGL201BZDIE

	To Download PI6CFGL201BZDIE Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .